In recent years, progressive research and development has been conducted on variable resistance nonvolatile memory devices having memory cells that use so-called variable resistance elements (hereinafter, also simply referred to as “nonvolatile memory devices”). A variable resistance element is an element that has a property of changing its resistance value according to an electrical signal, and enables information to be written due to such a change in the resistance value.
One structure of memory cells that use variable resistance elements is a crosspoint structure. In the crosspoint structure, each memory cell is placed at a different one of crosspoints of orthogonally arranged bit lines and word lines so as to be interposed between a corresponding one of the bit lines and a corresponding one of the word lines. Conventionally, various configurations of a nonvolatile memory device having such a crosspoint structure have been proposed (Patent Literatures (PTLs) 1 to 6, Non-Patent Literature (NPL) 1, etc.).
PTL 1 discloses a nonvolatile memory device that uses bidirectional variable resistors as memory cells. PTL 1 discloses that a varistor, for example, is used for a diode of a memory cell, as a bidirectional nonlinear element, in order to reduce a so-called leakage current that flows into unselected cells. PTL 1 also discloses the crosspoint structure.
PTL 2 discloses a nonvolatile memory device including a three-dimensional crosspoint variable resistance memory cell array having a multilayer structure.
NPL 1 discloses a memory cell structure having a combination of a variable resistance film and a unidirectional diode. NPL 1 also discloses a multilayer structure.
PTL 3 discloses a multilayer memory structure in which memory cells including Zener diodes and variable resistance memory elements that can be rewritten with a bipolar voltage are used.
PTL 4 discloses a multilayer memory structure using memory cells including memory elements and unidirectional control elements.
PTL 5 discloses a nonvolatile memory that has a three-dimensional structure, and uses memory cells having polysilicon diodes and including variable-resistance memory elements (RRAMs) that can be rewritten with a unipolar voltage. As shown in FIG. 22, PTL 5 discloses a word line structure in which odd-layer word lines and even-layer word lines within the same array plane are respectively connected to different vertical wires (tree trunks). Here, odd-layer word lines and even-layer word lines in a certain array plane are respectively connected to different drive circuits via drivers. Further, a driver that selects odd-layer word lines and a driver that selects even-layer word lines in a certain array plane, and a driver that selects odd-layer word lines and a driver that selects even-layer word lines in an array plane adjacent to the certain array plane are each controlled by different control signals. It should be noted that although PTL 5 discloses the case of word lines, it is easily inferred that such a structure can be applied to bit lines rather than word lines.